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Happyboard Technical Specs

This page details the technical specs of the Happyboard.

Technical Overview

IO Capabilities

Hardware Architecture

The core of the Happyboard is the ATMega128L AVR processor. The ATMega128L is a RISC core with 128KB internal flash memory and 4KB of internal RAM. It operates at 3.3V and at a clock frequency of 8Mhz.

The AVR has an external memory bus that allows it to access 64KB of external memory. The 256 bytes just beyond the internal RAM are mapped to the FPGA, which contains a number of registers which manage the various IO devices. The FPGA is programmed with code that drives all the various IO devices, based off the settings in its registers. User functions for controlling the IO simply read/write to FPGA registers (see fpga.h). The FPGA is configured at bootup with code stored in the 1Mb flash (AT45DB011b).

A few other IO devices are on an SPI bus connected to the processor. This includes the Analog Inputs (MCP3008), current sensing (MCP3008), FPGA configuration flash (AT45DB011b). The remaining IO devices (LCD, buttons, frobknob, etc) are connected directly to the processor via GPIOs.